ARITHMETIC FOR COMPUTERS (Part 1)

Assalamualaikum and Hello everyone.

Let's start our discussion with Arithmetic for Computers.

This chapter will include with :

• Operations on Integers
• Floating point real numbers

INTEGER ADDITION

 Computers represent integers in binary (base2)

3 = 11, 4 = 100, 5 = 101, 30 = 11110

      + Natural since only two values are represented

• Addition, etc. take place as usual (carry the 1, etc.)

        

        17 = 10001

        +5 = 101

____________________

        22 = 10110

• Some old machines use decimal (base10) with only 0/1

30 = 011 000

– Unnatural for digial logic, implementation complicated & slow.

1st Grade: Decimal Addition

  1 111111

 43 = 00101011

+29 = 00011101

___________________

 72 = 01001000

• Overflow if result out of range

- Adding +ve and -ve operands,no overflow

- Adding two +ve operands

• Overflow if result sign is 1

- Adding two -ve operands

• Overflow if result sign is 0

INTEGER SUTRACTION

Add negation of second operand

           0 = 100000000

         -10 = 00001010

      _____________________

        -10 = 011110110

• Now, add the conventional way…

         -10 = 11110110

        +10 = 00001010

      ____________________

          0 = 100000000

• Overflow if result out of range

              - Subtracting two +ve or two -ve operands, no overflow

• Subtracting +ve from -ve operand

              - Overflow if result sign is 0

• Subtracting -ve from =ve operand

              - Overflow if result sign is 1

DEALING WITH OVERFLOW

•  Some languages ignore overflow
• Other languages require raising an exception

                - Use MIPS add, addi, sub instructuctions

                - On overflow, invoke exception handler

                - Save PC in exception program counter (EPC) register

                - Jump to predefined handler acccess

MULTIPLICATION'

If you use the last row in multiplication, you should get exactly the same result as using the first row (

after all they represent the same number.

DIVISION

Divisiion in MIPS. MIPS supports multiplication and division using existing hardware, primarily the ALU and shifter. MIPS needs one extra hardware component - a 64-bit register able to supportsll and sra instructions. The upper (high) 32 bits of the register contains the remainder resulting from division. This is moved into a register in the MIPS register stack (e.g., $t0) by the mfhi command. The lower 32 bits of the 64-bit register contains the quotient resulting from division. This is moved into a register in the MIPS register stack by the mflo command.

In MIPS assembly language code, signed division is supported by the div instruction and unsigned division, by the divu instruction. MIPS hardware does not check for division by zero. Thus, divide-by-zero exception must be detected and handled in system software. A similar comment holds for overflow or underflow resulting from division.

FP ADDER HARDWARE

• Much more complex than integer adder
• Doing it in one clock cycle would take too long
• Much longer than integer operations
• Slower clock would penalize all instructions

Name : MARMI'ATI AL - AZIMAH BINTI AZHARI

Matrix no : B031310334